Design Methodologies for Cloud Server SoC’s

The seminar is approved by the PhD Board and entitles attendees to ask for credit validation.

Please, get in touch with Prof. Piovaccari if you are willing to take the final exam. We remind you that a certificate / proof of passing a final exam is required in order to ask for credit validation. For further information about it visit the specific webpage HERE. 

ABSTRACT

Cloud providers and Systems companies are increasingly designing their own large SoC’s (System-on-a-Chip) to optimize cloud service performance and increase efficiency for their specific datacenter workloads. Designing these large SoC’s has created unique challenges, which has necessitated an evolution of the development teams and the methodologies used for developing the SoC’s and the servers. In the seminar we will discuss the characteristics of cloud server SoC’s, will show how the semiconductor industry has evolved over the past decades, will give a high-level overview of the state-of-the-art digital design flow. We will also discuss major design blocks found in server SoC’s such as Compute Engines, Embedded Memories, Interconnects and I/O Interfaces, and will highlight key aspects of the design of SoC’s and Systems that are particularly challenging and evolving such as Chip Floorplanning, Power Integrity, Advanced Packaging, Manufacturing Test, and Thermal Management. The seminar will cover many topics students may not have been exposed to, but the goal is to provide a high-level overview of digital chip design today. In closing, we will talk about future directions of cloud server SoC design and will give advice for the next generation of engineers entering the digital design field.

BIO

Thomas A. (Tom) Volpe is a SoC architect and designer with more than 30 years of experience in the semiconductor industry. He is currently working as a consultant and advisor in the IoT space. Previously, he was a Principal Architect at Amazon Web Services for the Inferentia and Trainium cloud machine learning ASICs and for other cloud networking, network virtualization, and storage SoCs. Prior to that, he was an architect, designer, and leader at Calxeda, Analog Devices, and Motorola. He has developed and brought to production numerous successful SoCs for a variety of industries/applications. Over his career, he has designed and architected microprocessors, microcontrollers, phase-locked loops, memory controllers, automotive networking controllers, DSP processors, low-power servers, on-chip and off-chip interconnect fabrics, network virtualization accelerators, network routers, storage controllers, and machine learning ASICs. He has a broad background across almost every facet of integrated circuit design and development including architecture, micro-architecture, RTL design, custom circuit design, design verification, FPGA emulation, synthesis, timing analysis, power analysis, physical design, design-for-test, manufacturing test, and validation. He has also directed the work of package design, PCB design, signal integrity, power integrity, and circuit reliability teams. He has worked closely with hardware, firmware and application software development teams to specify and develop full system solutions. Thomas received his BS in Electrical Engineering (with High Honors) from the University of Texas at Austin. He is a member of the IEEE, Eta Kappa Nu, and Tau Beta Pi. He holds over 100 granted patents and an additional 20 patents pending